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Product Specification
PE4304
Product Description
The PE4304 is a 75-ohm high-linearity, 6-bit RF Digital Step Attenuator (DSA) covering a 31.5 dB attenuation range in 0.5 dB steps. The PE4304 provides both a parallel (latched or direct mode) and serial CMOS control interface, operates on a single 3-volt supply and maintains high attenuation accuracy over frequency and temperature. It also has a unique control interface that allows the user to select an initial attenuation state at power-up. The PE4304 exhibits very low insertion loss and low power consumption. This functionality is delivered in a 4x4 mm QFN footprint. The PE4304 is manufactured on Peregrine's UltraCMOSTM process, a patented variation of silicon-on-insulator (SOI) technology on a sapphire substrate, offering the performance of GaAs with the economy and integration of conventional CMOS. Figure 1. Functional Schematic Diagram
Switched Attenuator Array RF Input RF Output
75 RF Digital Attenuator 6-bit, 31.5 dB, DC - 2.0 GHz Features * 75 impedance * Attenuation: 0.5 dB steps to 31.5 dB * Low distortion for CATV and multi-carrier applications * Flexible parallel and serial programming interfaces * Unique power-up state selection * Positive CMOS control logic * High attenuation accuracy and linearity over temperature and frequency * Very low power consumption * Single-supply operation * Packaged in a 20 lead 4x4 mm QFN Figure 2. Package Type
4x4 mm -20 Lead QFN
Parallel Control Serial Control Power-Up Control
6
3
Control Logic Interface
2
Table 1. Electrical Specifications @ +25 C, VDD = 3.0 V, Zo = 75
Parameter
Operation Frequency Insertion Loss
2
Test Conditions
Frequency
DC 1.2 GHz
Minimum
DC 30 10 -
Typical
Maximum
2000
Units
MHz dB dB dBm dBm dB s
1.4 34 52 13 -
1.8 (0.15 + 4% of attenuation setting) 1
Attenuation Accuracy 1 dB Compression3,4 Input IP31,2,4 Return Loss Switching Speed Notes: 1. 2. 3. 4.
Any Bit or Bit Combination
DC 1.2 GHz 1 MHz 1.2 GHz
Two-tone inputs up to +18 dBm
1 MHz 1.2 GHz DC 1.2 GHz
50% control to 0.5 dB of final value
Device Linearity will begin to degrade below 1Mhz Max input rating in Table 2 & Figures on Pages 4 to 6 for data across frequency. Note Absolute Maximum in Table 3. Measured in a 50 system. (c)2005 Peregrine Semiconductor Corp. All rights reserved. Page 1 of 11
Document No. 70-0066-03 www.psemi.com
PE4304
Product Specification
Figure 3. Pin Configuration (Top View)
GND C0.5 C1 C2 C4
Table 3. Absolute Maximum Ratings
Symbol
VDD VI
Parameter/Conditions
Power supply voltage Voltage on any input Storage temperature range Operating temperature Input power (50 ) ESD voltage (Human Body
Min
-0.3 -0.3 -65 -40
Max
4.0 VDD+ 150 85 24 500
Units
V V C C dBm V
20
19
18
17
16
C16 RF1 Data Clock LE
1 2 3 4 5 10
15
C8 RF2 P/S Vss/GND GND
TST TOP PIN VESD
20-lead QFN 4x4mm
Exposed Solder Pad
14 13 12 11
6
7
8
9
Table 4. DC Electrical Specifications
Parameter
VDD Power Supply Voltage IDD Power Supply Current Digital Input High 0.7xVDD 0.3xVDD 1
VDD
VDD
PUP1
PUP2
GND
Min
2.7
Typ
3.0
Max
3.3 100
Units
V A V V A
Table 2. Pin Descriptions
Pin No.
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 Paddle
Pin Name
C16 RF1 Data Clock LE VDD PUP1 PUP2 VDD GND GND Vss/GND P/S RF2 C8 C4 C2 GND C1 C0.5 GND
Description
Attenuation control bit, 16dB (Note 4). RF port (Note 1). Serial interface data input (Note 4). Serial interface clock input. Latch Enable input (Note 2). Power supply pin. Power-up selection bit, MSB. Power-up selection bit, LSB. Power supply pin. Ground connection. Ground connection. Negative supply voltage or GND connection(Note 3) Parallel/Serial mode select. RF port (Note 1). Attenuation control bit, 8 dB. Attenuation control bit, 4 dB. Attenuation control bit, 2 dB. Ground connection. Attenuation control bit, 1 dB. Attenuation control bit, 0.5 dB. Ground for proper operation
Digital Input Low Input Leakage
Exposed Solder Pad Connection The exposed solder pad on the bottom of the package must be grounded for proper device operation. Electrostatic Discharge (ESD) Precautions When handling this UltraCMOSTM device, observe the same precautions that you would use with other ESD-sensitive devices. Although this device contains circuitry to protect it from damage due to ESD, precautions should be taken to avoid exceeding the rate specified in Table 3. Latch-Up Avoidance Unlike conventional CMOS devices, UltraCMOSTM devices are immune to latch-up. Switching Frequency The PE4304 has a maximum 25 kHz switching rate. Resistor on Pin 1 & 3 A 10 k resistor on the inputs to Pin 1 & 3 (see Figure 5) will eliminate package resonance between the RF input pin and the two digital inputs. Specified attenuation error versus frequency performance is dependent upon this condition.
Document No. 70-0066-03 UltraCMOSTM RFIC Solutions
Note 1: Both RF ports must be DC blocked with an external series capacitor or held at 0 VDC. 2: Latch Enable (LE) has an internal 100 k resistor to VDD. 3: Connect pin 12 to GND to enable internal negative voltage generator. Connect pin 12 to VSS (-VDD) to bypass and disable internal negative voltage generator. 4. Place a 10 k resistor in series, as close to pin as possible.
(c)2005 Peregrine Semiconductor Corp. All rights reserved. Page 2 of 11
PE4304
Product Specification
Evaluation Kit
The Digital Attenuator Evaluation Kit board was designed to ease customer evaluation of the PE4304 Digital Step Attenuator. J9 is used in conjunction with the supplied DC cable to supply VDD, GND, and -VDD. If use of the internal negative voltage generator is desired, then do not connect -VDD (Black banana plug). If an external - VDD is desired, then apply -3V. J1 should be connected to the parallel port of a PC with the supplied ribbon cable. The evaluation software is written to operate the DSA in serial mode, so Switch 7 (P/S) should be ON with all other switches off. Using the software, enable or disable each attenuation setting to the desired combined attenuation. The software automatically programs the DSA each time an attenuation state is enabled or disabled. To evaluate the Power up options, first disconnect the parallel ribbon cable from the evaluation board. The parallel cable must be removed to prevent the PC parallel port from biasing the control pins to unknown states. During power up in serial mode (P/ S=1 and LE=0) or in parallel mode with P/S=0 and LE=1, the default power-up signal attenuation is set to the value present on the six control bits on the six parallel data inputs (C0.5 to C16). This allows any one of the 64 attenuation settings to be specified as the power-up state. To power up in Parallel mode (P/S=0) with LE=0, the control bits are automatically set to one of four possible values. These four values are selected by the two power-up control bits, PUP1 and PUP2, as shown in the Parallel PUP Truth Table (Table 6).
Figure 4. Evaluation Board Layout
Peregrine Specification 101/0112
Figure 5. Evaluation Board Schematic
Peregrine Specification 102/0142
Note: Resistors on pins 1 and 3 are required to avoid package resonance and meet error specifications over frequency.
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PE4304
Product Specification
Typical Performance Data @ 25C, VDD = 3.0 V (unless otherwise specified) Figure 6. Insertion Loss Figure 7. Attenuation at Major steps
0
35 31.5dB
30 -1 25 Insertion Loss (dB) -2 Attenuation (dB)
20 16dB 15 0.5dB 1dB 2dB 8dB 4dB
-3
10 -4 5 -5 0 400 800 1200 1600 2000 0 0
400
800
1200
1600
2000
RF Frequency (MHz)
RF Frequency (MHz)
Figure 8. Input Return Loss at Major Attenuation Steps
0 -5 -10 Input Return Loss (dB) -15 -20 8dB -25 -30 -35 -40 0 400 800 1200 1600 2000 16dB 31.5dB
Figure 9. Output Return Loss at Major Attenuation Steps
0
-5
-10 Return Loss (dB)
-15
-20
-25
-30 -35 0 400 800 1200 1600 2000
RF Frequency (MHz)
RF Frequency (MHz)
(c)2005 Peregrine Semiconductor Corp. All rights reserved. Page 4 of 11
Document No. 70-0066-03 UltraCMOSTM RFIC Solutions
PE4304
Product Specification
Typical Performance Data @ 25C, VDD = 3.0 V (unless otherwise specified) Figure 10. Attenuation Error Vs. Frequency Figure 11. Attenuation Error Vs. Attenuation Setting
0.5
1
0.5
0.25
10MHz 250MHz
Attenuation Error (dB)
0 8dB -0.5 16dB
Attenuation Error (dB)
0 510MHz -0.25 750MHz -0.5
-1
31.5dB
1010MHz 1210MHz
-1.5
-0.75
-2 0 400 800 1200 1600 2000
-1 0 5 10 15 20 25 30 35 40
RF Frequency (MHz)
Attenuation Setting (dB)
Figure 12. Attenuation Error Vs. Attenuation Setting
0.6
Figure 13. Attenuation Error Vs. Attenuation Setting
0.4
0.4 Attenuation Error (dB)
10MHz, -40C
0.2
Error 510 Mhz
0.2
10MHz, 25C
0
500MHz, -40C
10MHz, 85C 0
-0.2
500MHz, 25C
500MHz, 85C
-0.2
-0.4
-0.4 0 5 10 15 20 25 30 35 40
-0.6 0 5 10 15 20 25 30 35 40
Attenuation Setting (dB)
10Mhz error 85
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PE4304
Product Specification
Typical Performance Data @ 25C, VDD = 3.0 V (unless otherwise specified) Figure 14. Attenuation Error Vs. Frequency Figure 15. Input IP3 Vs. Frequency
0.2
0.2
0
0
Attenuation Error (dB)
-0.2
Attenuation Error (dB)
-0.2
-0.4
1000MHz, -40C 1000MHz, 25C
-0.4 1200MHz, -40C 1200MHz, 25C -0.8 1200MHz, 85C
-0.6 1000MHz, 85C -0.8
-0.6
-1 0 5 10 15 20 25 30 35 40
-1 0 5 10 15 20 25 30 35 40
Attenuation Setting (dB)
Attenuation Setting (dB)
Figure 16. Input 1dB Compression (Major attenuation states, 50 System)
40 35 30 Compression (dB)
Figure 17. Input IP3 Vs. Frequency (Major attenuation states, 50 System)
60 55 50 Input IP3 (dBm) 45 40 35 30 25 20
25 20 15 10 5 0 0 400 800 1200 1600 2000
0
400
800
1200
1600
2000
RF Frequency (MHz)
RF Frequency (MHz)
(c)2005 Peregrine Semiconductor Corp. All rights reserved. Page 6 of 11
Document No. 70-0066-03 UltraCMOSTM RFIC Solutions
PE4304
Product Specification
Programming Options
Parallel/Serial Selection Either a parallel or serial interface can be used to control the PE4304. The P/S bit provides this selection, with P/S=LOW selecting the parallel interface and P/S=HIGH selecting the serial interface. Parallel Mode Interface The parallel interface consists of five CMOScompatible control lines that select the desired attenuation state, as shown in Table 5. The parallel interface timing requirements are defined by Figure 19 (Parallel Interface Timing Diagram), Table 9 (Parallel Interface AC Characteristics), and switching speed (Table 1). For latched parallel programming the Latch Enable (LE) should be held LOW while changing attenuation state control values, then pulse LE HIGH to LOW (per Figure 19) to latch new attenuation state into device. For direct parallel programming, the Latch Enable (LE) line should be pulled HIGH. Changing attenuation state control values will change device state to new attenuation. Direct Mode is ideal for manual control of the device (using hardwire, switches, or jumpers).
Clock, and Latch Enable (LE). The Data and Clock inputs allow data to be serially entered into the shift register, a process that is independent of the state of the LE input. The LE input controls the latch. When LE is HIGH, the latch is transparent and the contents of the serial shift register control the attenuator. When LE is brought LOW, data in the shift register is latched. The shift register should be loaded while LE is held LOW to prevent the attenuator value from changing as data is entered. The LE input should then be toggled HIGH and brought LOW again, latching the new data. The timing for this operation is defined by Figure 18 (Serial Interface Timing Diagram) and Table 8 (AC Characteristics). Power-up Control Settings The PE4304 always assumes a specifiable attenuation setting on power-up. This feature exists for both the Serial and Parallel modes of operation, and allows a known attenuation state to be established before an initial serial or parallel control word is provided. When the attenuator powers up in Serial mode (P/ S=1), the six control bits are set to whatever data is present on the six parallel data inputs (C0.5 to C16). This allows any one of the 64 attenuation settings to be specified as the power-up state. When the attenuator powers up in Parallel mode (P/ S=0) with LE=0, the control bits are automatically set to one of four possible values. These four values are selected by the two power-up control bits, PUP1 and PUP2, as shown in Table 6 (Power-Up Truth Table, Parallel Mode).
Table 5. Truth Table
P/S
0 0 0 0 0 0 0 0
C16
0 0 0 0 0 0 1 1
C8
0 0 0 0 0 1 0 1
C4
0 0 0 0 1 0 0 1
C2
0 0 0 1 0 0 0 1
C1
0 0 1 0 0 0 0 1
Attenuation C0.5 State
0 1 0 0 0 0 0 1 Reference Loss 0.5 dB 1 dB 2 dB 4 dB 8 dB 16 dB 31.5 dB
Table 6. Parallel PUP Truth Table
P/S
0 0 0 0
LE
0 0 0 0 1
PUP2
0 1 0 1 X
PUP1
0 0 1 1 X
Attenuation State
Reference Loss 8 dB 16 dB 31 dB Defined by C0.5-C16
Note: Not all 64 possible combinations of C0.5-C16 are shown in table
Serial Interface The serial interface is a 6-bit serial-in, parallel-out shift register buffered by a transparent latch. It is controlled by three CMOS-compatible signals: Data,
0 Note:
Power up with LE=1 provides normal parallel operation with C0.5-C16, and PUP1 and PUP2 are not active.
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PE4304
Product Specification
Figure 18. Serial Interface Timing Diagram
LE
Table 7. 6-Bit Attenuator Serial Programming Register Map
Clock
B5 C16
B4 C8
B3 C4
B2 C2
B1 C1
B0 C0.5
Data
MSB
LSB
MSB (first in)
tLESUP tLEPW
LSB (last in)
tSDSUP
tSDHLD
Figure 19. Parallel Interface Timing Diagram
LE
Parallel Data C16:C0.5
tPDSUP
tLEPW
tPDHLD
Table 8. Serial Interface AC Characteristics
VDD = 3.0 V, -40 C < TA < 85 C, unless otherwise specified Symbol
fClk tClkH tClkL tLESUP tLEPW tSDSUP tSDHLD Note:
Table 9. Parallel Interface AC Characteristics
VDD = 3.0 V, -40 C < TA < 85 C, unless otherwise specified Symbol
tLEPW tPDSUP tPDHLD
Parameter
Serial data clock frequency (Note 1) Serial clock HIGH time Serial clock LOW time LE set-up time after last clock falling edge LE minimum pulse width Serial data set-up time before clock rising edge Serial data hold time after clock falling edge
Min
Max
10
Unit
MHz ns ns ns ns ns ns
Parameter
LE minimum pulse width Data set-up time before rising edge of LE Data hold time after falling edge of LE
Min
10 10 10
Max
Unit
ns ns ns
30 30 10 30 10 10
fClk is verified during the functional pattern test. Serial programming sections of the functional pattern are clocked at 10 MHz to verify fclk specification.
(c)2005 Peregrine Semiconductor Corp. All rights reserved. Page 8 of 11
Document No. 70-0066-03 UltraCMOSTM RFIC Solutions
PE4304
Product Specification
Figure 20. Package Drawing
4.00 INDEX AREA 2.00 X 2.00 -B2.00
2.00 0.25 C -A0.10 C 0.08 C 0.020 0.20 REF EXPOSED PAD & TERMINAL PADS SEATING PLANE 0.80 4.00 -C2.00 TYP 0.50 TYP 0.55 2.00 1.00
5 11
0.435 0.18 1.00 EXPOSED PAD 0.23 1 0.10 CAB 2.00
1 15 20 16 6 10
0.435
0.18
4.00
DETAIL A
DETAIL A
2
1. Dimension applies to metallized terminal and is measured between 0.25 and 0.30 from terminal tip. 2. Coplanarity applies to the exposed heat sink slug as well as the terminals. 3. Dimensions are in millimeters.
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PE4304
Product Specification
Figure 21. Marking Specifications
4304 YYWW ZZZZZ
YYWW = Date Code ZZZZZ = Last five digits of PSC Lot Number
Figure 22. Tape and Reel Drawing
Table 10. Ordering Information
Order Code
4304-01 4304-02 4304-00 4304-51 4304-52
Part Marking
4304 4304 PE4304-EK 4304 4304
Description
PE4304-20MLP 4x4mm-75A PE4304-20MLP 4x4mm-3000C PE4304-20MLP 4x4mm-EK PE4304G-20MLP 4x4mm-75A PE4304G-20MLP 4x4mm-3000C
Package
20-lead 4x4 mm QFN 20-lead 4x4 mm QFN Evaluation Kit Green 20-lead 4x4 mm QFN Green 20-lead 4x4 mm QFN
Shipping Method
75 units / Tube 3000 units / T&R 1 / Box 75 units / Tube 3000 units / T&R
(c)2005 Peregrine Semiconductor Corp. All rights reserved. Page 10 of 11
Document No. 70-0066-03 UltraCMOSTM RFIC Solutions
PE4304
Product Specification
Sales Offices
The Americas Peregrine Semiconductor Corp.
9450 Carroll Park Drive San Diego, CA 92121 Tel 858-731-9400 Fax 858-731-9499
North Asia Pacific Peregrine Semiconductor K.K.
5A-5, 5F Imperial Tower 1-1-1 Uchisaiwaicho, Chiyoda-ku Tokyo 100-0011 Japan Tel: +81-3-3502-5211 Fax: +81-3-3502-5213
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Commercial Products: Batiment Maine 13-15 rue des Quatre Vents F- 92380 Garches, France Tel: +33-1-47-41-91-73 Fax : +33-1-47-41-91-73 Space and Defense Products: 180 Rue Jean de Guiramand 13852 Aix-En-Provence cedex 3, France Tel: +33(0) 4 4239 3361 Fax: +33(0) 4 4239 7227
South Asia Pacific Peregrine Semiconductor
28G, Times Square, No. 500 Zhangyang Road, Shanghai, 200122, P.R. China Tel: +86-21-5836-8276 Fax: +86-21-5836-7652
For a list of representatives in your area, please refer to our Web site at: www.psemi.com
Data Sheet Identification
Advance Information
The product is in a formative or design stage. The data sheet contains design target specifications for product development. Specifications and features may change in any manner without notice. The information in this data sheet is believed to be reliable. However, Peregrine assumes no liability for the use of this information. Use shall be entirely at the user's own risk. No patent rights or licenses to any circuits described in this data sheet are implied or granted to any third party. Peregrine's products are not designed or intended for use in devices or systems intended for surgical implant, or in other applications intended to support or sustain life, or in any application in which the failure of the Peregrine product could create a situation in which personal injury or death might occur. Peregrine assumes no liability for damages, including consequential or incidental damages, arising out of the use of its products in such applications. The Peregrine name, logo, and UTSi are registered trademarks and UltraCMOS is a trademark of Peregrine Semiconductor Corp.
Preliminary Specification
The data sheet contains preliminary data. Additional data may be added at a later date. Peregrine reserves the right to change specifications at any time without notice in order to supply the best possible product.
Product Specification
The data sheet contains final data. In the event Peregrine decides to change the specifications, Peregrine will notify customers of the intended changes by issuing a DCN (Document Change Notice).
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